1. Field of the Invention
The present disclosure generally relates to the field of fabricating integrated circuits, and, more particularly, to forming electronic fuses for providing device internal programming capabilities in complex integrated circuits.
2. Description of the Related Art
In modern integrated circuits, a very high number of individual circuit elements, such as field effect transistors in the form of CMOS, NMOS, PMOS elements, resistors, capacitors and the like, are formed on a single chip area. Typically, feature sizes of these circuit elements are steadily decreasing with the introduction of every new circuit generation, to provide currently available integrated circuits with an improved degree of performance in terms of speed and/or power consumption. A reduction in size of transistors is an important aspect in steadily improving device performance of complex integrated circuits, such as CPUs. The reduction in size is commonly associated with an increased switching speed, thereby enhancing signal processing performance. In addition to the large number of transistor elements, a plurality of passive circuit elements, such as capacitors, resistors and the like, are typically formed in integrated circuits that are used for a plurality of purposes.
Due to the decreased dimensions of circuit elements, not only the performance of the individual transistor elements may be improved, but also their packing density may be increased, thereby providing the potential for incorporating increased functionality into a given chip area. For this reason, highly complex circuits have been developed, which may include different types of circuits, such as analog circuits, digital circuits and the like, thereby providing entire systems on a single chip (SoC).
In such modern integrated circuits, minimal features sizes have now reached approximately 50 nm and less, thereby providing the possibility of incorporating various functional circuit portions at a given chip area, wherein, however, the various circuit portions may have a significantly different performance, for instance with respect to lifetime, reliability and the like. For example, the operating speed of a digital circuit portion, such as a CPU core and the like, may depend on the configuration of the individual transistor elements and also on the characteristics of the metallization system, which may include a plurality of stacked metallization layers so as to comply with a required complex circuit layout. Thus, highly sophisticated manufacturing techniques may be required in order to provide the minimum critical feature sizes of the speed critical circuit components. For example, sophisticated digital circuitry may be used on the basis of field effect transistors which represent circuit components in which the conductivity of a channel region is controlled by a gate electrode that is separated from the channel region by a thin dielectric material. Performance of the individual field effect transistors is determined by, among other things, the capability of the transistor to switch from a high impedance state into a low impedance state at high speeds, wherein a sufficiently high current may also have to be driven in the low impedance state. This drive current capability is determined by, among other things, the length of the conductive channel that forms in the channel region upon application of an appropriate control voltage to the gate electrode. For this reason, and in view of the demand for increasing the overall packing density of sophisticated semiconductor devices, the channel length, and thus the length of the gate electrode, is continuously being reduced, which in turn may require an appropriate adaptation of the capacitive coupling of the gate electrode to the channel region. Consequently, the thickness of the gate dielectric material may also have to be reduced in order to maintain controllability of the conductive channel at a desired high level. However, the shrinkage of the gate dielectric thickness may be associated with an exponential increase of the leakage currents, which may directly tunnel through the thin gate dielectric material, thereby contributing to enhanced power consumption and thus waste heat, which may contribute to sophisticated conditions during operation of the semiconductor device. Moreover, charge carriers may be injected into the gate dielectric material and may also contribute to a significant degradation of transistor characteristics, such as threshold voltage of the transistors, thereby also contributing to pronounced variability of the transistor characteristics over the lifetime of the product. Consequently, reliability and performance of certain sophisticated circuit portions may be determined by material characteristics and process techniques for forming highly sophisticated circuit elements, while other circuit portions may include less critical devices, which may thus provide a different behavior over the lifetime compared to critical circuit portions. Consequently, the combination of the various circuit portions in a single semiconductor device may result in a significantly different behavior with respect to performance and reliability, wherein the variations of the overall manufacturing process flow may also contribute to a further discrepancy between the various circuit portions.
For these reasons, in complex integrated circuits, frequently, additional mechanisms may be implemented so as to allow the circuit itself to adapt performance of certain circuit portions to comply with performance of other circuit portions, for instance upon completing the manufacturing process and/or during use of the semiconductor device, for instance when certain critical circuit portions may no longer comply with corresponding performance criteria, thereby requiring an adaptation of certain circuit portions, such as re-adjusting an internal voltage supply, resetting overall circuit speed and the like.
For this purpose, so-called electronic fuses, or e-fuses, may be provided in the semiconductor devices, which may represent electronic switches that may be activated once in order to provide a desired circuit adaptation. Hence, the electronic fuses may be considered as having a high impedance state, which may typically also represent a “programmed” state, and may have a low impedance state, typically representing a non-programmed state of the electronic fuse. Since these electronic fuses may have a significant influence on the overall behavior of the entire integrated circuit, a reliable detection of the non-programmed and the programmed state may have to be guaranteed, which may have to be accomplished on the basis of appropriately designed logic circuitry. Furthermore, since typically these electronic fuses may be actuated once over the lifetime of the semiconductor device under consideration, a corresponding programming activity may have to ensure that a desired programmed state of the electronic fuse is reliably generated in order to provide well-defined conditions for the further operational lifetime of the device.
For these reasons, appropriate mechanisms have been established so as to provide electronic fuses that may be programmed in a reliable manner. The programming of electronic fuses may rely on a degradation mechanism of a conductive material wherein, upon applying a current pulse, an irreversible change of the electronic characteristics of the electronic fuse may result in a reliably detectable programming status of the electronic fuse. To this end, electromigration, typically a non-desired effect in semiconductor devices, may be taken advantage of in order to provide a mechanism for permanently damaging the conductive line and thus achieving a detectable high impedance state. Electromigration is a phenomenon that can be observed in conductors, in which a sufficiently high current density may be established such that the collective movement of electrons in the conductor material may result in a material migration caused by the momentum transfer from the electrons to the atoms or ions of the material. Electromigration can typically be observed in conductor lines of semiconductor devices in which the conductive lines are embedded in a dielectric material that provides sufficient heat dissipation capability, thereby enabling very high current densities before excessive heat in the conductive line may result in irreversible damage, as may typically be observed in isolated conductors. Thus, although embedding the conductive lines in dielectric materials may allow operation of the semiconductor devices with high current densities, the material migration in the conductive lines caused by the momentum transfer of electrons may finally result in a degradation and thus failure of the conductive line during the operational lifetime of the semiconductor device. For this reason, electromigration effects in metallization systems of semiconductor devices are carefully studied and monitored in order to estimate performance and reliability of complex semiconductor devices. Electromigration, on the other hand, may be efficiently used in electronic fuses in order to intentionally initiate a degradation of a conductive line or fuse body so as to obtain a detectable high impedance state. To this end, the electromigration in metal silicide materials formed in silicon-based materials, such as polysilicon materials, may be efficiently used for providing electronic fuses in the device level of semiconductor devices, wherein the overall lateral dimensions and the material composition of the basic semiconductor material, in combination with the characteristics of the metal silicide, may thus have a significant influence on the overall performance of a corresponding electronic fuse. To this end, in addition to appropriate designs and layouts of corresponding electronic fuses based on silicon material and metal silicide, appropriate peripheral circuitry has also been developed, for instance in the form of transistor elements for driving the required current pulse through the electronic fuse so as to “blow” the fuse upon programming the electronic fuse, wherein the current drive capability of the transistor or transistors, and thus the size thereof, may have to be adapted to the current density required for programming the electronic fuse.
Upon further reducing the overall dimensions of circuit elements in sophisticated semiconductor devices, the gate length of field effect transistors is also reduced, which represents one important circuit element in complex semiconductor devices, thereby requiring efficient mechanisms for controlling the current flow in the channel region of the field effect transistors, as discussed above. Conventionally, electrode structures may be provided on the basis of a polysilicon material in combination with a metal silicide formed therein, which may be provided on an appropriate gate dielectric material, such as silicon dioxide, which separates the gate electrode from the channel region. In order to provide a very efficient overall manufacturing process flow, the electronic fuses may be formed together with the gate electrode structures of the transistors, since, as discussed above, polysilicon in combination with a metal silicide may provide an efficient mechanism for electronic fuses. With the introduction of gate lengths of 40 nm and less, however, it turns out that conventional gate electrode structures based on polysilicon, in combination with conventional gate dielectrics, such as silicon dioxide, silicon oxynitride and the like, may no longer be sufficient for appropriately controlling the channel in sophisticated field effect transistors. For this reason, conventional gate dielectric materials may be replaced, at least partially, by so-called high-k dielectric materials, i.e., dielectric materials having a dielectric constant of 10.0 or higher, in order to provide sufficient capacitive coupling of the gate electrode to the channel region without further increasing the resulting gate leakage currents. Concurrently, the polysilicon material may be replaced by a material of superior conductivity, which may also significantly reduce or avoid the creation of a depletion zone in the vicinity of the gate dielectric material. Consequently, a plurality of manufacturing strategies have been developed, one of which may be referred to as a gate replacement approach. In this very promising manufacturing technique, the gate electrode structure may initially be formed on the basis of polysilicon in combination with a conventional gate dielectric material or on the basis of a high-k dielectric material and the processing may be continued by completing the basic transistor configuration, i.e., forming drain and source regions and the like. In a very advanced manufacturing stage, the gate electrode structures may be embedded in a dielectric material and the polysilicon material may be removed by appropriate selective etch strategies. Thereafter, any appropriate metal species may be formed in the resulting gate openings in order to adjust the appropriate gate characteristics in terms of work function, conductivity and the like.
Although this manufacturing strategy may provide superior field effect transistors having high-k metal gate electrode structures, at the same time, the polysilicon material of non-transistor elements may be removed, such as the semiconductor material of the electronic fuses, which is then replaced by a highly conductive electrode metal, thereby, however, significantly changing the overall electronic behavior of the electronic fuses. That is, due to the superior conductivity, increased current densities may be required, which in turn may be associated with the provision of transistors of significantly increased size in order to provide the required high current values. On the other hand, reducing the overall lateral dimensions of the electronic fuses may be less than desirable, since typically it is extremely difficult to further reduce the critical dimensions in the device level on the basis of given lithography and patterning abilities of the circuit design under consideration.
In view of this situation, other strategies have been developed, such as providing the electronic fuses in the metallization system of the semiconductor device, which, however, may suffer from similar problems with respect to the required high current densities, due to the superior conductivity of the metal lines and vias in the metallization system of sophisticated semiconductor devices. In other approaches, electronic fuses may be formed in the active semiconductor layer, i.e., in the crystalline semiconductor material, in which the drain and source regions of the transistor elements may also be provided. In this manner, the gate replacement approach does not interfere with the electronic characteristics of the electronic fuses formed in the active semiconductor layer, wherein, however, it has been observed that corresponding electronic fuses may not efficiently operate in “bulk” configurations, that is, in semiconductor devices in which the active semiconductor material may be formed directly on the crystalline semiconductor material of the substrate without providing a buried insulating material, as is the case in an SOI (silicon-on-insulator) configuration.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.